1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, particularly, to a method of manufacturing a semiconductor device comprising gate electrodes of differing work functions.
2. Description of the Related Art
In recent years, it is has become of highest importance to lower the resistance of the gate electrode in accordance with the development of a MOSFET device of the sub-micron order. It was customary in the past to use a polycrystalline silicon (polysilicon) doped with an impurity for forming the gate electrode. However, a depletion layer is generated at the interface between the gate electrode formed of a polycrystalline silicon doped with an impurity and the gate insulating film. The generation of the depletion layer is substantially equal to an increase in the thickness of the gate insulating film so as to decrease the drive current of transistor. With progress in the miniaturization of the gate insulating film, the decrease of the drive current brings about a problem that cannot be neglected.
For suppressing the generation of the depletion layer in the gate electrode, it is effective to use a gate electrode made of a metal in place of a polycrystalline silicon. Also, the metal gate electrode has a work function corresponding to the mid band gap of silicon. Therefore, it is possible to use the metal gate electrode as a single gate electrode that permits forming symmetrical threshold voltages in, for example, the NMOS region and the PMOS region.
However, in the CMOS device comprising a metal gate electrode as, for example, a single gate electrode, the flat band voltage is decreased in each of the NMOS device region and the PMOS device region, which gives rise to the phenomenon that the threshold voltage is increased. For lowering the threshold voltage, it is possible to form a buried channel by means of a counter doping. In this case, however, the short channel effect of the MOSFET device is increased, which makes it impossible to achieve a fine device.
Such being the situation, it is proposed to form metal gates differing from each other in the work function in, for example, the NMOS region and the PMOS region of the CMOS structure. To be more specific, a method of forming a dual metal gate for a semiconductor device is disclosed in, for example, Japanese Patent Disclosure (Kokai) No. 2002-198441. The method for forming the dual metal gate disclosed in this prior art comprises preparing a semiconductor substrate including a PMOS region and an NMOS region and having a dummy gate formed in each of the PMOS region and the NMOS region, forming an interlayer insulating film on the semiconductor substrate in a manner to cover the dummy gates, polishing the interlayer insulating film until the dummy gates are exposed to the outside, forming a first trench defining a first metal gate by selectively removing any one of the dummy gates formed in the PMOS region and the NMOS region, successively forming a first gate insulating film and a first metal film on the entire region of the semiconductor substrate having the first trench formed therein, forming a first metal gate within the first trench by etching the first metal film and the first gate insulating film until the interlayer insulating film is exposed to the outside, forming a second trench defining a second metal gate region by removing the residual dummy gate, successively forming a second gate insulating film and a second metal film on the entire region of the semiconductor substrate having the second trench formed therein, and forming a second metal gate within the second trench by etching the second metal film and the second gate insulating film until the interlayer insulating film is exposed to the outside.
However, in the method disclosed in Japanese Patent Disclosure No. 2002-198441 quoted above, the first trench is formed by removing one dummy gate, followed by burying the first gate insulating film and the first metal gate in the first trench. Then, the second trench is formed by removing the residual dummy gate, followed by burying the second gate insulating film and the second metal gate in the second trench so as to form a dual metal gate. What should be noted is that, in this prior art, it is necessary to carry out twice the step of forming a gate insulating film so as to make the manufacturing process complex. What should also be noted is that, since the first metal gate is exposed to the outside in the step of forming the second gate insulating film, the reliability of the second gate insulating film is lowered. Further, if the second gate insulating film is formed under high temperatures not lower than 600° C., the exposed second metal gate tends to be deteriorated.